In serial data communications, a clock signal is recovered from an incoming stream of serial data. The recovered clock signal must be synchronized to the incoming data. The recovered clock signal can then be used for clocking or "retiming" the incoming data. Clock and data recovery circuits known in prior art use a phase-lock loop circuit to generate the recovered clock signal. Prior art circuits, however, tend to drift when there are few transitions in the incoming data stream. Transitions, or "edges" are essential to adjusting the clock phase to synchronize to the incoming data. For this reason, most systems require at least a minimum density of transitions in the data. One way to ensure sufficient transitions is to encode the serial data, for example using the 8b/10b encoding as specified in the Fibre Channel protocol. Such encoding is expensive in that it requires extra encoding circuitry at the transmission end, and conversely decoding circuitry at the receiver. More importantly, such encoding exacts a substantial penalty in bandwidth. What is needed is improved methods and apparatus for serial data and clock recovery in high-speed serial data communication systems.
Accordingly, one object of the present invention is to improve stability and reliability of data and clock recovery in high-speed serial data communication systems.
Another object of the invention is to reduce dependence upon transitions in the serial data stream for clock recovery.
A further object is to increase effective bandwidth of a serial channel by relaxing special data encoding requirements.
A still further object is to provide an improved clock and data recovery circuit for use in a semiconductor integrated circuit serial communications channel.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment which proceeds with reference to the appended drawings.